In modern integrated-circuit design, it is possible to integrate digital, analog, and RF circuitry onto a single chip. As a result of such integration, however, digital circuitry can inject noise through the common substrate that affects the sensitive analog and RF circuitry. This substrate noise coupling can severely degrade the performance of noise-sensitive circuits. Accordingly, substrate-noise-coupling analysis is becoming an important part of the design flow of integrated circuits. Typically, the effects of substrate coupling at low frequencies (e.g., up to 2–3 GHz) can be verified by computing the substrate resistances between all circuit parts that inject noise into the substrate or that are sensitive to noise.
Some of the most commonly used methods to analyze substrate noise coupling involve costly trial-and-error procedures due to the lack of an efficient substrate-network extractor for practical circuits. Consequently, integrated-circuit designs are often delayed and engineering time increased. To solve this problem, other techniques have been proposed for computing substrate noise coupling.
For instance, some known techniques involve a detailed numerical analysis of substrate noise coupling. In one approach, a device simulator is used to obtain a full numerical simulation of currents and potentials in the substrate. In this method, the entire substrate is discretized, or meshed, into smaller data points, thereby creating large resistance and capacitance matrices. The mesh definition plays an important role in this technique because it involves a tradeoff between accuracy and computational efficiency. Consequently, this technique is impractical for large circuit designs.
Another known method for calculating the substrate network is the so-called boundary-element method (“BEM”). The BEM requires meshing only for the contacts and results in a small, but dense, Z matrix. In order to calculate substrate resistances, the inverse Z matrix has to be computed. Dense matrix inversion, however, has a computational complexity of O(N3) where N is the matrix dimension. Consequently, this method is computationally intensive for large circuit designs.
Another technique (the “preprocessed BEM”), involves first obtaining Z parameters from polynomial curve fitting. This method provides a simpler estimation of Z parameters, but requires models for different geometries and spacings to be computed and stored in a design-tool library. These libraries have to be adapted to each process. Accordingly, the preprocessed BEM is not efficient for large designs.
An alternate approach to these methods uses a scalable resistance-based model for substrate-resistance extraction. In one such approach, a scalable resistance-based model is used to predict substrate noise coupling between contacts in a heavily doped or lightly doped CMOS process. This scalable model, however, was developed for two contacts using a two-port resistive model, and cannot be used for multiple contacts or account for three-dimensional variations in contact architecture.